registe.rs
Explore, decode, and manipulate CPU registers across architectures
What is registe.rs?
A comprehensive web-based toolset for working with low-level CPU registers, designed for systems programmers, kernel developers, and hardware engineers. Currently supporting ARM64 (AArch64) with more architectures coming soon.
🔍 Register Explorer
Search and edit CPU registers with full bitfield visualization. Supports multiple simultaneous registers with URL-based state sharing.
💥 Exception Decoder
Decode exception syndrome registers (ESR, FAR, SPSR) into human-readable explanations. Perfect for analyzing crash dumps.
📄 Page Table Editor
Build and decode page table entries with embedded register editors for TCR and MAIR configuration.
⚙️ Feature Explorer
Visualize architectural features across ARMv8/ARMv9 versions and CPU implementations. Compare optional and mandatory features.
Supported Architectures
ARM64 (AArch64)
✅ Available Now
ARMv7-M
🚧 Coming Soon
x86 / x86-64
🚧 Coming Soon
RISC-V
🚧 Coming Soon
Technology
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